Short CV/Education and training

  • Piedad Brox born in 1979, holds a Doctor of Science in Microelectronics (with honors) from University of Seville (Spain, 2009).

  • She obtained two post-doctoral fellowships funded by Spanish Government and University of Seville. She belongs to Digital and Mixed Integrated Circuits Design (UDDM) group since 2002, and she became a Tenured Scientist in 2018 at the IMSE (CSIC/University of Seville).

  • Her experience during these years in the design of digital integrated circuits for different application purposes has been applied in the area of hardware security more recently (last 9 years). Her expertise in this area includes scientific works with RO PUFs on MPSoC devices, PUFs extracted from SRAMs implemented on several CMOS integration technologies (TSMC 90nm, UMC 65 nm), hybrid (sw/hw) realizations of post-quantum cryptographic algorithms, and the VLSI realization of trusted virtual sensors using lightweight authenticated ciphers.

  • She has led 4 research projects funded in competitive calls, and currently, she is the coordinator of two on-going projects (SPIRS funded by European Commission and ARES funded by Spanish Government).

Selected publications

  • M.C. Martínez-Rodríguez, E. Camacho-Ruiz, P. Brox and S. Sánchez-Solano. “A Configurable RO-PUF for Securing Embedded Systems Implemented on Programmable Devices”, Electronics, vol. 10, no. 16, article 1957, 2021. Available at here (Q2 (Electrical and Electronics Engineering, FI: 2.397. SJR® 2020).

  • M.C. Martínez-Rodríguez, M. A. Prada-Delgado, P. Brox, I. Baturone. “VLSI Design of Trusted Virtual Sensors”. Sensors, vol. 18, no. 2, article 347, 2018 MDPI. DOI: 10.3390/s18020347 ISSN: 1424-8220 (Q1, FI: 3.275. PR: 15/64, 22/86, 77/265. JCR® 2019).

  • E. Calvo-Gallego, P. Brox, S. Sánchez-Solano. “Low-cost dedicated hardware IP modules for background subtraction in embedded vision systems”. Journal of Real-Time Image Processing, vol. 12, no. 4, pp. 681-695, 2016. DOI: 10.1007/s11554-014-0455-5 (Q2, FI: 2.01. PR: 109/260, 54/133, 11/17. JCR® 2016).

  • P. Brox, M.C. Martínez-Rodríguez, E. Tena-Sánchez, I. Baturone, A. J. Acosta-Jiménez. “Application speficic integrated circuit solution for multi-input multi-output piecewiseaffine Functions”. International Journal of Circuit Theory and Applications, vol. 44, no. 1, pp. 4-20, 2016. DOI: 10.1002/cta.2058. (Q3, FI: 1.571. PR: 144/260. JCR® 2016, Q2, FI: 0.384. PR: 265/1377. SJR®2016).

  • P. Brox, I. Baturone, S. Sánchez-Solano. “Edge-adaptive Spatial Video De-interlacing Algorithms Based on Fuzzy Logic”. IEEE Transactions on Consumer Electronics, vol. 60, no. 3, pp. 375-383, 2014. DOI 10.1109/TCE.2014.6937321 (Q3, FI: 1.045. PR: 135/244, 122/635. JCR® 2014, Q1, FI: 0.941. PR: 122/635, 8/43. SJR® 2014).

  • M.C. Martínez-Rodríguez, P. Brox, I. Baturone. “Digital VLSI Implementation of Piecewise-Affine Controllers Based on Lattice Approach”. IEEE Transactions on Control Systems Technology, vol 23, no. 3, pp. 842-854, 2015. DOI: 10.1109/TCST.2014.2345094. (Q1, FI: 2.818. PR: 30/255, 6/59. JCR® 2015, Q1, FI:2.986. PR: 19/1536, 6/598. SJR® 2015).

  • P. Brox, I. Baturone, S. Sánchez-Solano. “Fuzzy logic-based embedded system for video de-interlacing”. Applied Soft Computing, vol. 14, Part C, pp. 338-346, 2014. DOI: 10.1016/j.asoc.2013.01.015. (Q1, FI: 2.81. PR: 17/123, 14/102. JCR® 2014).

  • P. Brox, J. Castro, M.C. Martínez-Rodríguez, C.J. Jiménez, I. Baturone, A. Acosta. “A Programmable and Configurable ASIC to Generate Piecewise-Affine Functions Defined Over General Partitions”. IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 60, no. 12, pp. 3182-3194, 2013. DOI: 10.1016/j.asoc.2013.01.015. (Q1, FI: 2.679. PR: 20/121, 14/102. JCR® 2013).

  • S. Sánchez-Solano, E. del Toro, M. Brox, P. Brox, I. Baturone. ”Model-Based Design Methodology for Rapid Development of Fuzzy Controllers on FPGAs”. IEEE Transactions on Industrial Informatics, vol. 9, no. 3, pp. 1361-1370, 2013. DOI: 10.1109/TII.2012.2211608. (Q1, FI: 8.785. PR: 1/59, 1/102, 1/43. JCR® 2013).

  • M. Brox, S. Sánchez-Solano, E. del Toro, P. Brox, F. J. Moreno-Velo. “CAD Tools for Hardware Implementation of Embedded Fuzzy Systems on FPGAs”. IEEE Transactions on Industrial Informatics, vol. 9, no. 3, pp. 1635-1644, 2013. DOI: 10.1109/TII.2012.2228871. (Q1, FI: 8.785. PR: 1/59, 1/102, 1/43. JCR® 2013).



Complete list of publications

Selected projects

  • Secure Platform for ICT systems Rooted at the Silicon manufacturing process (SPIRS). IP: Piedad Brox Jiménez. Grant Agreement number 952622. / H2020-SU-ICT-2019 call of H2020 program. Global Budget: 5.041.091M€. CSIC Budget: 930.690€. Consortium: CSIC, Tampere University, CEA, Thales, Telefónica I+D+i, LINKS, Politecnico Di Torino, NEC, NEXT srl. Period: 2021 – 2024.

  • PID2020-116664RB-I00, Design, Implementation and Validation of Attack-Resistant hardware Roots-of-Trust for secure Embedded Systems (ARES). PI: Piedad Brox Jiménez / Carlos J. Jiménez. Programa Estatal de Investigación, Desarrollo e Innovación Orientada a los Retos de la Sociedad. Convocatoria 2020. Budget: 146.410€. Period: 2021-2025.

  • LINKA2016, Advancing in cybersecurity technologies. PI: Piedad Brox Jiménez. Proyecto financiado por la convocatoria pública competitiva del programa de movilidad i-LINK financiado por el CSIC. Budget: 23.738€. Period: 2020-2021.

  • TEC2017-83557-R, Diseño de Soluciones Hardware para Gestionar con Confianza, Seguridad y Privacidad la Identidad de las Personas y Cosas en el Marco de la IoT (HW-IDENTIoTY). PI: Piedad Brox Jiménez / Iluminada Baturone Castillo. Programa Estatal de Investigación, Desarrollo e Innovación Orientada a los Retos de la Sociedad. Convocatoria 2017. Budget: 139.150€. Participation: Investigadora principal. Period: 2018 – 2020.

  • TEC2014-57971-R, Diseño de hardware cripto-biométrico para cifrado y autenticación de vídeo (IDE-EO). PI: Piedad Brox Jiménez / Iluminada Baturone Castillo. Programa Estatal de Investigación, Desarrollo e Innovación Orientada a los Retos de la Sociedad. Convocatoria 2014. Budget: 187.550€. Participation: Investigadora principal. Period: 2015 – 2017.

Membership in scientific bodies/juries

  • Participation in Scientific Committees: 9th International Conference on Distributed Smart Cameras (ICDSC) 2015, 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2012

Media coverage

Additional qualifications

  • Post-doc scholarship (Juan de la Cierva) funded by Spanish Government, 2010 – 2012

  • Post-doc scholarship funded by University of Seville, 2013 – 2017


Soft Skills/Other activities and achievements

Other activities and achievements/family

  • Maternity in 2017


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